1. Field of the Invention
The present disclosure relates to the technology of low temperature poly-silicon, more specifically, to a method for adjusting the threshold voltage of LTPS TFT.
2. Description of the Related Art
The Low Temperature Poly-silicon (“LTPS”, hereinafter) productions require Vth (the threshold voltage or gate voltage) of the P-type device and the N-type device be symmetric with the voltage of 0V. The advantage of it thereof is that the switch effect of the circuit is relatively obvious. The condition of abnormal in switching is not likely to be occurred. However, in the practical productive process, the condition that Vth is small caused by the left avertence of the I-V curve of the N-type device is likely to be occurred, which will further cause the problem that Vth of the P-type device is not symmetric with that of the N-type device.
An LTPS device as shown in FIG. 1A-FIG. 1B, a buffer layer of Nitride 11 (SiNx) and Oxide 12 (SiOx) is formed over Substrate 10. Poly-silicon 13 is formed on the local area of Oxide 12. In the current processes, the etching process generally comprises the following two steps. The first step is etching Metal Layer 16 (M1) and Nitride (SiNx) Layer 15 by dry etching in the Inductively Coupled Plasma mode with SF6 gas and O2 gas and by utilizing a Photoresist 17. Meanwhile, Oxide (SiOx) layer will be over etched in a small amount; as the critical dimension of the device, which is acquired after Metal Layer 16 and Nitride 15 are etched, needs to be considered, the amount of over etching is very little. In the follow-up technical field, the amount of over etching can be ignored. The second step is etching the Metal Layer 16 by Cl2 and O2 to form the Expected Metal Gate 16′. The SiNx layer and the SiOx layer will not be etched in this step, so that the shape of SiNx and SiOx shown in the figure is formed. The disadvantages of the process is that as follows: The SiOx layer can not be etched sufficiently, which causes the ions not to pass through Oxide 14 and not to be implanted into Poly-silicon 13, and the threshold voltage Vth is not easy to adjust. The advantage factor is shown by the dotted line in FIG. 1C, the practical threshold voltage is smaller than the expected normal threshold voltage.
Chinese Patent No. CN101852893A discloses a method for performing deep etching on silicon dioxide by taking photo-resist as a mask. The method comprises the following steps of: 1, preparing a photo-resist mask on the surface of a silicon dioxide sample; 2, heating the photo-resist mask in a gradient mode to harden the mask; and 3, etching the silicon dioxide sample by an ICP dry method. The method for performing the deep etching on the silicon dioxide by taking the photo-resist as the mask has the advantages of simple and fast process, high selection ratio, capability of achieving an etching depth of 25 microns, good etching appearance, steep side wall and the like.
Chinese Patent No. CN1560657 uses a compound masking technology combining the metal film and photoetching glue layer, realizes the deep etching process to the silicon dioxide. The invention uses photoetching glue and it generates no attaching particles in reaction ion etching process, and the etching selection rate is high of Cr, Al, NI metal masking films when F contained plasma is used to etch the silicon dioxide. It solves the deficiencies that the etched surface is coarse, radio frequency polarization can not too high, and the speed is slow in mask film etching process with metal film, at the same time, it can avoid the negative caused by using the single photoetching glue. The other character of the invention is: the thickness of the demanded metal film and the photoetching glue is less than the thickness in only using one of then, it can reduce the difficulty of filming process and etching process and the cost, upgrades the photoetching yield and the minimal figure resolution, and it can be realized easily.
U.S. Patent No. 2007/0249182 A1 disclosed a method for etching the silicon dioxide. Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100 DEG C. and 350 DEG C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20 DEG C. and 200 DEG C., and etching the wafer with an oxide to nitride selectivity greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a an inductively coupled plasma processing chamber by applying a bias power to the wafer, applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20 DEG C. and 200 DEG C., and etching the wafer with an oxide to nitride selectivity greater than 10:1. Consequently, the above invention did not solve the problem that the practical threshold voltage is smaller than the expected normal threshold voltage.